nextOpcode macros:
	65C816										| RISC-V					| ARM
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	Note: RAM is 8-bits wide. regPC is held in Zero (direct) page and is 32-bits	| a7, regPC, ptrJ are all 32-bit registers.	| regPC, ptrJ are aliases for
		wide. All '816 code lives in bank 0, so a 16-bit index is all that's	| ptrJ holds the address of the jump-table to	| registers.
		required.								| handle each decoded opcode.			|
========================================================================================|===============================================|==================================
.local  incH										|						|
											|						|
lda     [regPC]         ; Load 16-bit value from 24-bit address         ( 7)		| lbu	a7,(regPC)	# Fetch next byte	| ldrb    r0,[regPC],#1		@ Fetch byte at PC, Increment PC
and     #$00FF          ; We only want the bottom 8-bits...             (+3)		|						|
asl                     ; Double for indexing in 16-bit wide jump table (+2)		| slli	regZ,a7,2	# *4 for index		| ldr     pc,[ptrJ, r0, lsl #2]	@ Take byte in r0, << 2, add to ptrJ
tax                     ; X used to index into jump table               (+2)		| add	regZ,regZ,ptrJ	# Form offset 		|				@ fetch that word, transfer into PC.
											|						|
; Increment the PC									|						|
											|						|
inc     regPC+0                 ; Low word                              (+7)		| inc	regPC   				|
beq     incH                    ; 2 cycles + 1 when branch taken        (+2) = 23	|						|
											|						|
jmp     (opcodeJumpTable,x)     ;                                       (+6) = 29	| lw	regZ,(regZ)	# Fetch address		|
											| jalr	x0,0(regZ)	# Jump to it		|
											|						|
incH:											|						|
inc     regPC+2                 ; Top word                              (23 + 1 + 7)	|						|
jmp     (opcodeJumpTable,x)     ;                                       (+6) = 37	|						|